ECE 105L Design, Synthesis and Optimization Lab

The Lab sessions will be synchronized with the relevant topics covered in ECE 105:

Defining the Integrated Chip (IC) specifications for Analog, Digital and Mixed signal designs and the methodologies implemented for each desired system, from a simple idea into the Pre-Synthesis phase including IC verification concepts and Optimization flow.

The given lab sessions will be using advanced electronic design automation (EDA) software to create the different testbenches needed.