ECE 106 Placement, Routing and Power Estimation

The course will focus on defining the Physical Implementation Flow, Place and Route, Parasitic extraction, Design Timing Reports, Power Analysis, and the full layout of the Integrated Chip (IC) as a continuation of the topics covered in ECE 105 / ECE 105L

The given topics will be synchronized with the relevant lab sessions covered in ECE 106L using advanced electronic design automation (EDA) software.